Evaluate the six-pillar approach of Semicon 2.0 in addressing India's position in the global semiconductor value chain.

Approved by the Union Cabinet on 15 July 2026 with an outlay of ₹1,27,500 crore, Semicon 2.0 restructures India's chip strategy around six pillars—Design, Machines & Materials, More Fabs, ATMP/OSAT, R&D and Talent—shifting from one-off incentives to a full value-chain approach [1].

Strengths of the six-pillar design

• Whole-chain coverage: unlike ISM 1.0's fab-heavy focus, it addresses every value-chain node—from design IP to materials and packaging—reducing single-point import dependence [1].
• Moving up the ladder: an explicit node roadmap (28nm–110nm → 3nm/2nm) targets higher-value fabrication [1].
• Design leverage: builds on 105 startups/MSMEs given EDA-tool access, positioning India as a chip-design hub where it holds comparative advantage [1].
• Talent pipeline: 315 universities and 68,000 students trained address the sector's binding skill constraint [1].
• Continuity: rests on ISM 1.0 traction—Micron, Kaynes, CG Semi in commercial production; 10 projects worth ₹1.6 lakh crore across 6 states [1][2].

Limitations

• Downstream tilt: ATMP/OSAT and assembly are easier wins; leading-edge fabrication (2nm) remains capital- and technology-intensive, first fab only by 2028 [1].
• Upstream gaps: dependence on imported machines, ultra-pure materials and critical minerals persists.
• Scale: outlay is modest against Taiwan/Korea/US subsidies; execution and water/power infrastructure remain risks.

Overall, the six-pillar framework is a sound, holistically-designed instrument that rightly widens beyond fabs. Realising its promise of self-reliance by 2035 hinges on execution, sustained R&D funding and securing upstream inputs—aligning it firmly with Atmanirbhar Bharat.