What goals does Semicon 2.0 aim to achieve?

1. At a Glance

• Semicon 2.0 is the second phase of the India Semiconductor Mission (ISM), approved by the Union Cabinet on 15 July 2026 with an outlay of ₹1,27,500 crore [1][2].
• Launched alongside the Mobile Phone Manufacturing Scheme (MPMS) (₹62,500 crore outlay), it deepens India's push into chip fabrication, assembly/packaging, and electronics component manufacturing [3].
• UPSC relevance: tests static facts (ministries, outlays, ISM 1.0 vs 2.0) plus current-affairs application (Atmanirbhar Bharat, PLI-linked schemes, Make in India electronics).

2. Why in the News

• On 15 July 2026, the Union Cabinet cleared Semicon 2.0 and MPMS as part of a seven-decision package totaling ₹2,19,353 crore, alongside the National Investment Policy for Urea-2026 and railway/highway projects [2][3].
• The Gazette notification with detailed scheme guidelines is expected the following month (August 2026) [3].

3. Background & Evolution

• India Semiconductor Mission (ISM) — Phase 1: approved December 2021, outlay ₹76,000 crore [3].
• 2022 amendment: enabled up to 50% capital subsidy for large projects, e.g., Micron's memory chip packaging facility in Sanand, Gujarat [3].
• Phase 1 funds also flowed to the Electronics Component Manufacturing Scheme, incentivising smaller component manufacturing [3].
• By December 2025, 10 semiconductor projects worth ₹1.60 lakh crore stood approved across 6 states — silicon fabs, silicon carbide fabs, advanced/memory packaging, and assembly-testing infrastructure [1].
• Semicon 2.0 (Phase 2) approved 15 July 2026 — outlay ₹1,27,500 crore — to expand fabrication, assembly, and packaging capacity, and to advance design ecosystem and precision manufacturing [1][2][3].

4. Core Static Facts

5. Multi-Dimensional Analysis

Economic

• Targets over 30% of global mobile production share via MPMS; aims to nearly double India's cumulative mobile production to ~₹39 lakh crore, with exports rising to ~₹15 lakh crore [3].
• Expected to generate 5 lakh direct and 15 lakh indirect jobs [3].

Scientific/Technological

• Roadmap to indigenise 3nm and 2nm advanced chip nodes, moving beyond mature-node packaging/assembly focus of Phase 1 [1].
• Incentivises firms manufacturing machines/materials for semiconductor fabrication (equipment ecosystem), not just chips themselves [1].

Administrative/Governance

• Continuity with Phase 1 mechanism (capital subsidy model) but scaled up outlay; precise operational guidelines await Gazette notification (due August 2026) [3].
• Builds federal geographic spread — Phase 1 projects already span 6 states (e.g., Gujarat, Odisha, Punjab, Andhra Pradesh) [1].

Geopolitical/Strategic

• Part of India's strategy to reduce import dependence in semiconductors/electronics amid global supply-chain diversification away from China-centric manufacturing (Atmanirbhar Bharat framing).

6. Recent Developments (last 12–18 months)

• Dec 2025: 10 ISM-approved projects cumulatively worth ₹1.60 lakh crore across 6 states [1].
• 15 July 2026: Cabinet approves Semicon 2.0 (₹1.27 lakh crore) and MPMS (₹62,500 crore) as part of ₹2.19 lakh crore package [2][3].
• Aug 2026 (expected): Gazette notification detailing Semicon 2.0 operational guidelines [3].

7. Prelims Hooks

• Semicon 2.0 approved by Union Cabinet on 15 July 2026.
• Semicon 2.0 outlay: ₹1,27,500 crore.
• Companion scheme launched same day: Mobile Phone Manufacturing Scheme (MPMS), outlay ₹62,500 crore.
• ISM Phase 1 approved December 2021, outlay ₹76,000 crore.
• 2022 amendment allowed up to 50% capital subsidy for large fabrication/packaging projects.
• Micron's memory chip packaging facility is located in Sanand, Gujarat.
• Phase 1 funds also routed through the Electronics Component Manufacturing Scheme.
• As of December 2025, 10 semiconductor projects worth ₹1.60 lakh crore approved across 6 states.
• Semicon 2.0 sets a technology roadmap targeting 3nm and 2nm chip nodes.
• 105 startups are developing chips under India's semiconductor design ecosystem (as cited under ISM 2.0 factsheet).
• Total value of the 15 July 2026 seven-decision Cabinet package: ₹2,19,353 crore.
• Nodal ministry for ISM/Semicon 2.0: Ministry of Electronics and Information Technology (MeitY).
• Expected 5-year outcomes of Semicon 2.0/MPMS: ₹4 lakh crore investment, ₹2 lakh crore production, ₹1 lakh crore exports.
• Semicon 2.0/MPMS jointly projected to create 5 lakh direct and 15 lakh indirect jobs.

8. Mains Relevance

• GS-III: Indian Economy — Infrastructure; Science & Technology — indigenization of technology, developments in electronics/semiconductors.
• Syllabus heading: "Indian Economy and issues relating to planning, mobilization of resources"; "Awareness in the fields of IT, Space, Computers, Robotics, Nano-technology".
• Possible question stems: 1. "Discuss the significance of Semicon 2.0 in India's quest for self-reliance in semiconductor manufacturing. What structural challenges remain?" 2. "Compare Phase 1 and Phase 2 of the India Semiconductor Mission in terms of objectives, incentive structure, and outcomes." 3. "Semiconductor manufacturing is capital- and technology-intensive. Critically examine India's policy approach through PLI-linked schemes like ISM and MPMS."

9. Related Topics to Study Next

• Production Linked Incentive (PLI) Scheme — underlying incentive architecture MPMS/ISM build upon.
• Electronics Component Manufacturing Scheme — feeder scheme for component-level manufacturing.
• Design Linked Incentive (DLI) Scheme — supports chip design startups referenced under ISM 2.0.
• Atmanirbhar Bharat / Make in India — overarching policy umbrella.
• Global semiconductor supply chain diversification (China+1) — geopolitical driver.
• Micron Sanand project (Gujarat) — flagship Phase 1 case study.
• National Investment Policy for Urea-2026 — approved in the same Cabinet package, useful for current-affairs cross-linking.

10. Common Errors / Trap Areas

• Confusing ISM Phase 1 outlay (₹76,000 crore, 2021) with Semicon 2.0 outlay (₹1,27,500 crore, 2026).
• Mixing up Semicon 2.0 (chip fabrication/design) with MPMS (mobile phone assembly/component manufacturing) — they are distinct but simultaneously approved schemes.
• Assuming Semicon 2.0 is a standalone new scheme rather than Phase 2 of the existing ISM.
• Misattributing nodal ministry — it is MeitY, not MoEFCC or DPIIT.
• Treating the 3nm/2nm roadmap as already achieved rather than a stated target under Phase 2.