UPSC Prelims Practice Questions — Summit exploring challenges, opportunities in semiconductor industry to be held tomorrow

Q1. In the semiconductor value chain, which of the following activities fall in the back-end ATMP/OSAT segment, as distinct from chip design and front-end wafer fabrication?

  1. Sealing a cut-out die inside a protective housing and connecting it to external leads
  2. Transferring circuit patterns onto a silicon wafer by exposing it to light through a mask
  3. Checking finished chips electrically for defects before they are shipped
  4. Laying out a chip's logic architecture and IP blocks with software tools
  • A. 2 and 3 only
  • B. 1 and 3 only
  • C. 1, 3 and 4 only
  • D. 1, 2 and 3 only

Q2. Consider the following statements: Which of the following is correct in respect of the above statements?

  1. Adding a small amount of phosphorus to pure silicon increases its electrical conductivity.
  2. Phosphorus has five electrons available for bonding, so each phosphorus atom that takes a silicon atom's place in the lattice leaves one electron free to carry current.
  • A. Both Statement-I and Statement-II are correct and Statement-II explains Statement-I
  • B. Both Statement-I and Statement-II are correct, but Statement-II does not explain Statement-I
  • C. Statement-I is correct, but Statement-II is incorrect
  • D. Statement-I is incorrect, but Statement-II is correct

Q3. With reference to the stages of semiconductor production and the incentives India offers for them, consider the following statements: Which of the statements given above is/are correct?

  1. A chip-design firm supported under the Design Linked Incentive scheme can bring a product to market without owning a fab, by having its wafers made at a foundry.
  2. Chip design generally needs much more capital per project than wafer fabrication, which is why design-stage support is set higher than support for fabs.
  • A. 1 only
  • B. 2 only
  • C. Both 1 and 2
  • D. Neither 1 nor 2