Union Minister Shri Ashwini Vaishnaw interacts with Semiconductor Chip Design Companies approved under the DLI Scheme

1. At a Glance

• Design Linked Incentive (DLI) Scheme is the design-side pillar of the Semicon India Programme of MeitY, targeting fabless chip design startups/MSMEs. [S1][S2]
• The Union Minister's 27 Jan 2026 review set a fresh ambition: 50 fabless companies in the next phase, six prioritised design domains, and a new Deep Tech Awards instrument from 2026. [S1]
• Relevance: GS-III (Indigenisation of technology, Industrial policy, IT/electronics), and the broader Aatmanirbhar Bharat semiconductor strategy.

2. Why in the News

• On 27 January 2026, Union Minister for Electronics & IT Shri Ashwini Vaishnaw held a review interaction in New Delhi with chip-design companies approved under the DLI Scheme. [S1]
• Announcements: target of ≥50 fabless companies in the next phase; focus on six design domains — Compute Systems, RF, Networking, Power Management, Sensors, Memory; Deep Tech Awards to be instituted in 2026. [S1]

3. Background & Evolution

• Dec 2021 — Union Cabinet approved the Semicon India Programme with outlay of ₹76,000 crore (~US$10 bn); DLI scheme notified as one of four verticals. [S2]
• Other Semicon India verticals: Semiconductor Fabs, Display Fabs, Compound Semiconductors/ATMP/OSAT. [S2]
• DLI implementing/nodal agency: Centre for Development of Advanced Computing (C-DAC) under MeitY. [S2]
• Original target: nurture ≥20 domestic chip-design companies to reach ₹1,500 crore turnover in 5 years. [S2]
• 2025: Semicon India 2025 showcased DLI startups; India Semiconductor Mission 2.0 announced as successor scaling-up. [S2]

4. Core Static Facts

• Parent programme: Semicon India Programme. [S2]
• Ministry/Dept: Ministry of Electronics & IT (MeitY). [S1][S2]
• Nodal implementing agency: C-DAC (Centre for Development of Advanced Computing). [S2]
• Launch: December 2021. [S2]
• Semicon India outlay: ₹76,000 crore. [S2]
• Three DLI components: (i) Chip Design Infrastructure Support (C-DISC) — EDA tools, IP cores, design platforms; (ii) Product Design Linked Incentive — reimbursement of expenditure; (iii) Deployment Linked Incentive — incentive on net sales. [S2]
• Current cohort: 24 startups approved under DLI. [S2]
• VC funding attracted: ~₹430 crore. [S2]
• Six target design domains (Jan 2026): Compute Systems, RF, Networking, Power Management, Sensors, Memory. [S1]
• Next-phase target: ≥50 fabless semiconductor companies. [S1]
• Strategic application sectors: video surveillance, drone detection, energy metering, microprocessors, satellite communications, IoT SoCs. [S2]

5. Multi-Dimensional Analysis

Economic - Builds fabless ecosystem — high-IP, low-capex segment where India has a chance given large EDA workforce (≈20% of global chip-design talent). [S2] - Targets revenue scale (₹1,500 cr/firm in 5 yrs) and VC depth (₹430 cr already mobilised). [S2]

Strategic / Geopolitical - Reduces dependence on imported chips and on geopolitically concentrated foundries; complements US CHIPS Act, EU Chips Act and Quad semiconductor cooperation. [S1][S2] - Six chosen domains (RF, Networking, Power, Sensors, Memory, Compute) overlap with defence, 5G/6G, EVs, space — dual-use criticality. [S1]

Scientific / Technological - Tape-outs at advanced nodes via DLI cohort; access to EDA tools and foundry shuttle services via C-DAC. [S2] - Proposed Deep Tech Awards 2026 to incentivise frontier R&D (AI chips, quantum, photonics). [S1]

Administrative - Single-window via MeitY-C-DAC; verticals split between India Semiconductor Mission (ISM) (fabs) and DLI (design). [S2] - Scale-up risk: moving from 24 → 50+ firms needs deeper IP, mentorship and foundry shuttle access. [S1][S2]

6. Recent Developments (last 12-18 months)

• 27 Jan 2026 — Vaishnaw's review; 50-fabless target and six domains announced; Deep Tech Awards 2026 flagged. [S1]
• 2025 — Semicon India 2025 event; India Semiconductor Mission 2.0 announced. [S2]
• 2025 — Cabinet push under "Government pushes semiconductor design innovation with the DLI Scheme" communiqué. [S2]
• 2024 — Two more futureDESIGN start-ups onboarded under DLI. [S2]

7. Prelims Hooks

• DLI Scheme launched in December 2021 under the Semicon India Programme. [S2]
• Implementing ministry: MeitY (not DST, not DoT). [S1][S2]
• Nodal agency for DLI: C-DAC. [S2]
• Semicon India Programme outlay: ₹76,000 crore. [S2]
• DLI has three components: Chip Design Infrastructure, Product DLI, Deployment Linked Incentive. [S2]
• Original DLI target: 20 domestic companies, ₹1,500 cr turnover in 5 years. [S2]
• 2026 announcement: target ≥50 fabless companies in next phase. [S1]
• Six DLI focus domains (2026): Compute, RF, Networking, Power Management, Sensors, Memory. [S1]
• Deep Tech Awards to be instituted in 2026. [S1]
• Currently 24 startups supported under DLI; ₹430 cr VC mobilised. [S2]
• Sectoral coverage includes drone detection, energy metering, satellite communications, IoT SoCs. [S2]
• DLI sits alongside ISM-administered Fab, Display Fab, Compound Semi/ATMP/OSAT schemes. [S2]

8. Mains Relevance

• GS-III — Indigenisation of technology and developing new technology; Effects of liberalisation on the economy; Industrial policy.
• GS-II — Government policies and interventions in various sectors.
• Possible question stems: 1. "The Design Linked Incentive Scheme is a necessary but not sufficient condition for India's semiconductor sovereignty." Examine. 2. Discuss how India's fabless-first strategy under the Semicon India Programme leverages comparative advantage in chip design talent. 3. Evaluate the role of MeitY and C-DAC in nurturing a domestic deep-tech ecosystem with reference to DLI and proposed Deep Tech Awards 2026.

9. Related Topics to Study Next

• India Semiconductor Mission (ISM) — sister vertical handling fabs/ATMP.
• Production Linked Incentive (PLI) for electronics & IT hardware — demand-side complement.
• Compound Semiconductor / ATMP / OSAT scheme — assembly & packaging leg.
• National Quantum Mission, 2023 — deep-tech adjacency.
• National Policy on Electronics 2019 — overarching framework.
• Digital India / Aatmanirbhar Bharat — political-economy umbrella.
• US CHIPS & Science Act, EU Chips Act, Quad semiconductor supply-chain initiative — global context.
• C-DAC — institutional study (autonomous body under MeitY).

10. Common Errors / Trap Areas

• DLI is under MeitY, not DST or DoT; nodal agency is C-DAC, not ISM. [S1][S2]
• DLI ≠ PLI; DLI is design-side, PLI (electronics) is manufacturing-side.
• Semicon India outlay is ₹76,000 cr for the programme, not for DLI alone. [S2]
• The six domains announced in Jan 2026 (Compute/RF/Networking/Power/Sensors/Memory) are focus areas, not eligibility filters from launch. [S1]
• Original target 20 companies / ₹1,500 cr turnover; the 50-fabless number is a next-phase aspiration (Jan 2026), not the launch target. [S1][S2]

11. Sources

• [S1] Union Minister Shri Ashwini Vaishnaw interacts with Semiconductor Chip Design Companies approved under the DLI Scheme — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2219248 — (tier: 1)
• [S2] PIB compilation of DLI Scheme press releases (PRID 2002752, 2159727, 2163622, 1790346, 2039638; Press Note 156811; India Semiconductor Mission 2.0 Note 157237) — https://www.pib.gov.in/PressNoteDetails.aspx?NoteId=156811&ModuleId=3&reg=3&lang=1 — (tier: 1)