UPSC Prelims Practice Questions — Design Linked Incentive Scheme
Q1. With reference to the Design Linked Incentive (DLI) Scheme, consider the following:
1. Its nodal implementing agency is the Centre for Development of Advanced Computing (C-DAC).
2. Its administrative ministry is the Ministry of Heavy Industries.
3. It has a total outlay of ₹1,000 crore.
4. It runs over a tenure of 5 years.
Which of the above is/are correctly identified?
- Its nodal implementing agency is the Centre for Development of Advanced Computing (C-DAC).
- Its administrative ministry is the Ministry of Heavy Industries.
- It has a total outlay of ₹1,000 crore.
- It runs over a tenure of 5 years.
- A. 1, 3 and 4
- B. 1, 2 and 3
- C. 2 and 4 only
- D. 1 and 2 only
Q2. Consider the following statements comparing the institutional roles of C-DAC and the India Semiconductor Mission (ISM):
1. The DLI Scheme is implemented by C-DAC, whereas the overall Semicon India Programme is steered by the India Semiconductor Mission.
2. C-DAC is an R&D organisation under MeitY, whereas the India Semiconductor Mission is set up as an Independent Business Division within the Digital India Corporation.
3. Both C-DAC and the India Semiconductor Mission function under the Ministry of Heavy Industries.
Which of the statements given above is/are correct?
- The DLI Scheme is implemented by C-DAC, whereas the overall Semicon India Programme is steered by the India Semiconductor Mission.
- C-DAC is an R&D organisation under MeitY, whereas the India Semiconductor Mission is set up as an Independent Business Division within the Digital India Corporation.
- Both C-DAC and the India Semiconductor Mission function under the Ministry of Heavy Industries.
- A. 1 and 2 only
- B. 1 and 3 only
- C. 2 and 3 only
- D. 1, 2 and 3
Q3. Which of the following are correctly identified as schemes/components under the Semicon India Programme?
1. Scheme for setting up Semiconductor Fabs.
2. Scheme for setting up Display Fabs.
3. Design Linked Incentive Scheme.
4. Production Linked Incentive (PLI) Scheme for the Automobile and Auto Components industry.
Which of the above is/are correctly identified?
- Scheme for setting up Semiconductor Fabs.
- Scheme for setting up Display Fabs.
- Design Linked Incentive Scheme.
- Production Linked Incentive (PLI) Scheme for the Automobile and Auto Components industry.
- A. 1, 2 and 3
- B. 1, 3 and 4
- C. 2 and 4 only
- D. 1, 2, 3 and 4
Q4. Consider the following statements about the Semicon India Programme and its DLI component:
1. The Programme has an overall outlay of ₹76,000 crore, of which the DLI Scheme forms a ₹1,000 crore component.
2. The Programme extends 50% fiscal support of project cost for silicon-CMOS fabs but only 30% of capital expenditure for compound semiconductor and ATMP/OSAT facilities.
3. The Programme was approved by the Union Cabinet in December 2021.
Which of the statements given above is/are correct?
- The Programme has an overall outlay of ₹76,000 crore, of which the DLI Scheme forms a ₹1,000 crore component.
- The Programme extends 50% fiscal support of project cost for silicon-CMOS fabs but only 30% of capital expenditure for compound semiconductor and ATMP/OSAT facilities.
- The Programme was approved by the Union Cabinet in December 2021.
- A. 1 and 3 only
- B. 1 and 2 only
- C. 2 and 3 only
- D. 1, 2 and 3
Q5. Consider the following statements comparing the incentive components of the DLI Scheme:
1. Under the Product Design Linked Incentive, reimbursement is up to 50% of eligible expenditure, subject to a ceiling of ₹15 crore per application.
2. Under the Deployment Linked Incentive, the incentive is 6% to 4% of net sales turnover over 5 years, subject to a ceiling of ₹30 crore per application.
3. The Chip Design Infrastructure Support component provides a direct cash reimbursement of up to ₹30 crore per application.
Which of the statements given above is/are correct?
- Under the Product Design Linked Incentive, reimbursement is up to 50% of eligible expenditure, subject to a ceiling of ₹15 crore per application.
- Under the Deployment Linked Incentive, the incentive is 6% to 4% of net sales turnover over 5 years, subject to a ceiling of ₹30 crore per application.
- The Chip Design Infrastructure Support component provides a direct cash reimbursement of up to ₹30 crore per application.
- A. 1 and 2 only
- B. 1 and 3 only
- C. 2 and 3 only
- D. 1, 2 and 3
Q6. Which of the following are correctly identified as components of the DLI Scheme?
1. Chip Design Infrastructure Support — access to EDA tools, IP cores and design platforms via C-DAC.
2. Product Design Linked Incentive — reimbursement of a share of eligible design expenditure.
3. Deployment Linked Incentive — incentive linked to net sales turnover of deployed designs.
4. Fabrication Linked Incentive — 50% capital-expenditure support for setting up a semiconductor fab.
Which of the above is/are correctly identified?
- Chip Design Infrastructure Support — access to EDA tools, IP cores and design platforms via C-DAC.
- Product Design Linked Incentive — reimbursement of a share of eligible design expenditure.
- Deployment Linked Incentive — incentive linked to net sales turnover of deployed designs.
- Fabrication Linked Incentive — 50% capital-expenditure support for setting up a semiconductor fab.
- A. 1, 2 and 3
- B. 2, 3 and 4
- C. 1 and 4 only
- D. 1, 2, 3 and 4
Q7. Consider the following statements about the fabless segment of the semiconductor industry:
1. Fabless companies design chips but outsource their physical fabrication to foundries.
2. It is the foundry (fabrication) segment, rather than the fabless segment, that accounts for about 30–35% of global semiconductor sales.
3. Chip design, the core fabless activity, contributes up to 50% of the value addition in a chip.
Which of the statements given above is/are correct?
- Fabless companies design chips but outsource their physical fabrication to foundries.
- It is the foundry (fabrication) segment, rather than the fabless segment, that accounts for about 30–35% of global semiconductor sales.
- Chip design, the core fabless activity, contributes up to 50% of the value addition in a chip.
- A. 1 and 3 only
- B. 1 and 2 only
- C. 2 and 3 only
- D. 1, 2 and 3
Q8. The Design Linked Incentive Scheme, which targets India's fabless chip-design segment, is operationalised as its nodal agency by which one of the following?
- A. Centre for Development of Advanced Computing (C-DAC)
- B. Semiconductor Laboratory (SCL), Mohali
- C. Software Technology Parks of India (STPI)
- D. Digital India Corporation
Q9. In the context of the DLI Scheme's reported progress (e.g., '16 tape-outs'), the term 'tape-out' most precisely refers to which one of the following?
- A. The finalised integrated-circuit design handed over to a foundry for fabrication
- B. The post-fabrication testing of a chip for defects
- C. The packaging and assembly of a fabricated chip
- D. The filing of a patent for a chip design
Q10. Consider the following statements regarding the progress of the DLI Scheme:
1. The number of chip-design projects sanctioned under the scheme has risen from 23 to 24.
2. As per the latest backgrounder, DLI-supported projects have recorded 6 tape-outs and 16 ASICs.
3. DLI-supported projects have leveraged over three times the government incentive in private investment.
Which of the statements given above is/are correct?
- The number of chip-design projects sanctioned under the scheme has risen from 23 to 24.
- As per the latest backgrounder, DLI-supported projects have recorded 6 tape-outs and 16 ASICs.
- DLI-supported projects have leveraged over three times the government incentive in private investment.
- A. 1 and 3 only
- B. 1 and 2 only
- C. 2 and 3 only
- D. 1, 2 and 3
Q11. Consider the following entities claimed as eligible applicants under the DLI Scheme:
1. Domestic semiconductor design companies.
2. Startups engaged in semiconductor design.
3. MSMEs engaged in semiconductor design.
4. Foreign-owned semiconductor fabrication (foundry) units operating abroad.
Which of the above is/are NOT correctly identified as eligible beneficiaries?
- Domestic semiconductor design companies.
- Startups engaged in semiconductor design.
- MSMEs engaged in semiconductor design.
- Foreign-owned semiconductor fabrication (foundry) units operating abroad.
- A. 1 only
- B. 4 only
- C. 3 and 4 only
- D. 1 and 4 only
Q12. Under the Semicon India Programme steered by the India Semiconductor Mission, the DLI Scheme targets nurturing at least how many domestic chip-design companies to achieve a turnover exceeding ₹1,500 crore within five years?