UPSC Prelims Practice Questions — Chips to Start-up (C2S) Programme

Q1. With reference to the implementation architecture of the Chips to Start-up (C2S) Programme, consider the following statements. Which of the above is/are NOT correct?

  1. It is a programme of the Ministry of Electronics & Information Technology (MeitY).
  2. Bundled student designs are fabricated at the Semi-Conductor Laboratory (SCL), Mohali, on the 180 nm node.
  3. Student designs are aggregated and dispatched for fabrication roughly every three months.
  4. The Department of Telecommunications is the nodal ministry that funds and administers the programme.
  • A. 1 and 2
  • B. 2 and 3
  • C. 1, 2 and 3
  • D. 4 only

Q2. In the context of the C2S Programme, the 'ChipIN Centre' is best described as which one of the following?

  • A. A national chip-design hub set up and operated by C-DAC Bengaluru that provides shared access to commercial EDA tools, compute, IP cores and mentoring, and aggregates student designs for fabrication
  • B. A semiconductor fabrication foundry at Mohali that manufactures chips on the 180 nm node
  • C. An incentive-disbursing wing of MeitY that funds fabless start-ups on a deployment-linked basis
  • D. An inter-ministerial committee that clears semiconductor fabrication investment proposals

Q3. Under the Design Linked Incentive (DLI) Scheme of the Semicon India Programme, financial support is envisaged for approximately how many domestic companies, start-ups and MSMEs in semiconductor design?

  • A. 20
  • B. 50
  • C. 100
  • D. 175

Q4. The Semicon India Programme, with an outlay of ₹76,000 crore, under which the C2S Programme, DLI Scheme and ISM operate, was approved by the Union Cabinet in which year?

  • A. 2020
  • B. 2021
  • C. 2022
  • D. 2024

Q5. The Special Manpower Development Programme for Chips to System Design (SMDP-C2SD), the forerunner to the C2S Programme, was an initiative of which one of the following?

  • A. Ministry of Electronics & Information Technology
  • B. Department of Science & Technology
  • C. Department of Space
  • D. Defence Research and Development Organisation

Q6. Under the SMDP-C2SD, a centralized chip-design facility at C-DAC provided remote access to engineering students spread across how many academic institutions?

  • A. 32
  • B. 46
  • C. 60
  • D. 120

Q7. With reference to the C2S Programme, consider the following statements. Which of the statements given above is/are correct?

  1. It has a total outlay of ₹250 crore spread over five years.
  2. It aims to generate 85,000 industry-ready manpower at B.Tech, M.Tech and PhD levels.
  3. It is a capacity-building umbrella programme anchoring the design pillar of India's semiconductor strategy.
  4. It provides a deployment-linked financial incentive of 6% on net sales to fabless start-ups.
  • A. 1, 2 and 3
  • B. 1 and 4
  • C. 2, 3 and 4
  • D. 1, 3 and 4

Q8. Which one of the following, a premier R&D organisation under MeitY, is the implementing agency that operationalises the C2S Programme?

  • A. Centre for Development of Advanced Computing (C-DAC)
  • B. Society for Applied Microwave Electronics Engineering & Research (SAMEER)
  • C. Centre for Materials for Electronics Technology (C-MET)
  • D. National Institute of Electronics & Information Technology (NIELIT)

Q9. With reference to the cumulative achievements reported for the C2S Programme, consider the following statements. Which of the statements given above is/are correct?

  1. 56 student-designed chips have been fabricated, packaged and delivered.
  2. 122 design submissions have been received from 46 institutions.
  3. Around one lakh individuals from about 400 organisations have used the shared national EDA infrastructure.
  4. Over 5,000 fabless start-ups have received financial incentives for chip design under the programme.
  • A. 1, 2 and 3
  • B. 1 and 4
  • C. 2 and 4
  • D. 1, 2, 3 and 4

Q10. Fabrication and packaging of the 56 student-designed chips reported under the C2S Programme were carried out at which one of the following facilities?

  • A. Semi-Conductor Laboratory (SCL), Mohali
  • B. Gallium Arsenide Enabling Technology Centre (GAETEC), Hyderabad
  • C. Society for Integrated Circuit Technology and Applied Research (SITAR), Bengaluru
  • D. SAMEER, Mumbai

Q11. As per the reported performance of the C2S Programme, how many shared wafer runs has the ChipIN Centre completed?

  • A. 3
  • B. 6
  • C. 46
  • D. 56

Q12. With reference to the three pillars of India's semiconductor design and manufacturing strategy, consider the following statements. Which of the above is/are NOT correct?

  1. The C2S Programme is a capacity-building initiative nurturing chip-design manpower and start-ups in academic institutions.
  2. The DLI Scheme provides a product design linked incentive of up to 50% of eligible expenditure to fabless domestic companies.
  3. The India Semiconductor Mission (ISM) is the specialised, independent body driving long-term semiconductor and display ecosystem strategy.
  4. The DLI Scheme is administered by NITI Aayog as its nodal agency.
  • A. 1 and 2
  • B. 2 and 3
  • C. 3 only
  • D. 4 only