India Semiconductor Mission seeks to build an end-to-end chip ecosystem. Critically evaluate the gap between design capability and fabrication capacity in India's current semiconductor push.

The India Semiconductor Mission (ISM), under MeitY, envisions a full "design-to-fabrication" chip value chain. Yet India's strengths remain concentrated in design and talent, while advanced fabrication capacity lags — a structural asymmetry the current push must reconcile.

Emerging design capability

• Robust talent and IP base: SCL Mohali's shared wafer runs enabled 122 chip designs from 46 institutions and 75+ patent filings [1].
• Democratised access: NIELIT and SCL made an indigenous 1.2 µm PDK available on eChipHub, targeting training of ~30,000 students in chip design [1].
• India already hosts a large share of global VLSI design workforce, supporting a fabless ecosystem.

The fabrication gap

• SCL Mohali's node (~1.2 µm) is a legacy/mature node, far from commercial nanometre-scale nodes — suited to teaching and prototyping, not high-performance chips.
• Capacity is thin: hence the government's ₹4,500 crore modernisation of SCL, targeting a ~100x rise in wafer output while ruling out privatisation [2].
• Heavy import dependence on foreign PDKs, EDA tools, materials and equipment persists.

Bridging measures

• Convergence of skilling (NIELIT) and public fabrication (SCL) plus private fabs (Tata, Micron) under ISM builds both ends simultaneously [1].
• Domestic PDKs reduce reliance on foreign design ecosystems, advancing Atmanirbhar Bharat [1].

The design–fabrication gap is real but narrowing. Sustained investment in advanced-node fabs, EDA indigenisation and academia–fab linkages can convert India's design edge into genuine end-to-end self-reliance, realising ISM's vision of a resilient semiconductor economy.