NIELIT and SCL Mohali Collaborate to Make Indigenous 1.2 µm Process Design Kit Available on eChipHub

Now I have enough grounded facts (4+ from Tier-1 PIB sources). Writing the study note.

NIELIT–SCL Mohali Collaboration: Indigenous 1.2 µm PDK on eChipHub

1. At a Glance

• NIELIT and SCL Mohali (both autonomous bodies under MeitY) have made an indigenous 1.2 µm Process Design Kit (PDK) available on eChipHub, a national semiconductor design education platform. [S1]
• Advances objectives of the India Semiconductor Mission (ISM) by giving students, researchers, startups, MSMEs, and industry access to a complete "design-to-fabrication" workflow using homegrown chip technology. [S1]
• High-yield UPSC topic: sits at intersection of Digital India, Atmanirbhar Bharat in electronics, and semiconductor self-reliance — a recurring Prelims/Mains theme since 2021.
• Tests recall of institutional architecture (NIELIT vs SCL vs ISM) — a common source of confusion. [S1]

2. Why in the News

• PIB press release dated 23 July 2026 announced the operational availability of the 1.2 µm PDK on eChipHub, formalising a collaboration whose MoU was signed earlier. [S1]

3. Background & Evolution

• 25 April 2025: NIELIT and SCL Mohali signed an MoU, witnessed by Shri S. Krishnan, MeitY Secretary, laying the foundation for this collaboration. [S1]
• eChipHub was jointly developed by NIELIT with SoCTeamup Semiconductors Pvt. Ltd., and is implemented and managed by NIELIT. [S1]
• 28 November 2025: Government announced ₹4,500 crore for modernization of SCL Mohali, explicitly ruling out privatisation, and targeting a ~100x increase in wafer production capacity; two facilities — the Semiconductor Process Gallery and Abhyuthanam Training Block — were inaugurated. [S2]
• SCL Mohali has separately conducted six shared wafer runs, enabling 122 chip design submissions from 46 institutions, resulting in 75+ patent filings and 500+ IP cores/ASICs/SoC designs under development — indicating an established academia-fab linkage prior to the PDK release. [S1]
• This builds on the broader India Semiconductor Mission, under which SCL Mohali's modernisation is meant to support government-backed EDA tools for ~300 universities. [S2]

4. Core Static Facts

5. Multi-Dimensional Analysis

Economic - Aims to build a domestic fabless chip design talent pool, reducing long-term import dependence on foreign EDA/PDK ecosystems. [S1] - Supports MSMEs and startups by lowering entry barriers to chip design (free/subsidised access via a national platform). [S1]

Scientific/Technological - 1.2 µm is a mature/legacy node (not leading-edge), appropriate for teaching, prototyping, and low-complexity ASIC/analog design, not high-performance computing chips. - Enables genuine design-to-fabrication cycle domestically, rather than design-only exposure. [S1]

Administrative/Governance - Demonstrates inter-institutional convergence between two MeitY autonomous bodies (NIELIT for skilling, SCL for fabrication) plus a private co-developer (SoCTeamup) — a public-private-autonomous body model. [S1] - Aadhaar-based authentication reflects use of India Stack digital infrastructure for controlled access to strategic technology. [S1]

Strategic - Reduces reliance on foreign PDKs (e.g., from TSMC, GlobalFoundries ecosystems) for basic design education, aligning with Atmanirbhar Bharat in a dual-use (civilian-strategic) technology domain.

6. Recent Developments (last 12–18 months)

• 25 April 2025: NIELIT–SCL Mohali MoU signed. [S1]
• 28 November 2025: ₹4,500 crore SCL Mohali modernisation announced; Semiconductor Process Gallery and Abhyuthanam Training Block inaugurated; Punjab asked to allocate 25 acres for expansion. [S2]
• 23 July 2026: 1.2 µm PDK made live on eChipHub under the NIELIT–SCL collaboration. [S1]

7. Prelims Hooks

• NIELIT = National Institute of Electronics and Information Technology; autonomous scientific society under MeitY. [S1]
• NIELIT holds "Deemed to be University" status. [S1]
• NIELIT headquartered at Ropar, Punjab, with 11 constituent campuses. [S1]
• SCL = Semiconductor Laboratory, located at Mohali, autonomous body under MeitY. [S1]
• eChipHub developed jointly by NIELIT and SoCTeamup Semiconductors Pvt. Ltd. [S1]
• eChipHub PDK access uses Aadhaar-based authentication. [S1]
• MoU between NIELIT and SCL signed on 25 April 2025, witnessed by MeitY Secretary S. Krishnan. [S1]
• The PDK released is of 1.2 micron (µm) process node — indigenous. [S1]
• NIELIT targets training ~30,000 students in semiconductor design via this initiative. [S1]
• SCL Mohali modernisation budget: ₹4,500 crore, announced 28 November 2025. [S2]
• Government explicitly committed SCL Mohali will not be privatised. [S2]
• SCL's shared wafer runs so far: 6 runs, 122 chip designs, 46 institutions, 75+ patents. [S1]
• The umbrella national programme referenced is the India Semiconductor Mission (ISM). [S1]
• SCL modernisation targets ~100x increase in wafer production capacity. [S2]

8. Mains Relevance

• GS-III: Science & Technology — indigenisation of technology, developments in electronics/semiconductor sector; also Indian Economy — infrastructure, industrial policy (Atmanirbhar Bharat).
• GS-II: Government policies and interventions for sectors (education/skilling via autonomous bodies), issues arising from design and implementation of institutional mechanisms.
• Possible Mains stems: 1. "Examine the significance of indigenous Process Design Kits (PDKs) in reducing India's dependence on foreign semiconductor design ecosystems. Discuss the role of institutions like NIELIT and SCL in this effort." (GS-III) 2. "India Semiconductor Mission seeks to build an end-to-end chip ecosystem. Critically evaluate the gap between design capability and fabrication capacity in India's current semiconductor push." (GS-III) 3. "Discuss how convergence between skilling institutions and public fabrication facilities can accelerate technology self-reliance in strategic sectors." (GS-II/III)

9. Related Topics to Study Next

• India Semiconductor Mission (ISM) — the umbrella scheme this initiative advances.
• Semiconductor Laboratory (SCL) Mohali — history, 2021 fire incident, modernisation trajectory.
• Digital India / Atmanirbhar Bharat — broader policy context for indigenisation.
• Production Linked Incentive (PLI) scheme for electronics/semiconductors — related industrial policy tool.
• India Semiconductor Mission fabs (Tata, Micron, CG Power etc.) — private sector fab investments under ISM.
• NIELIT's broader mandate — IT literacy, skilling programmes (compare with NIC, C-DAC).
• EDA (Electronic Design Automation) tools access for universities — linked capacity-building initiative under SCL modernisation.

10. Common Errors / Trap Areas

• Don't confuse NIELIT (skilling/education body) with C-DAC (Centre for Development of Advanced Computing) — both under MeitY but different mandates.
• Don't confuse SCL Mohali (a government fab, MeitY) with private fabs under ISM (e.g., Tata Electronics, Micron) — SCL is much older (est. 1976 originally at Chandigarh) and state-owned.
• 1.2 µm is a legacy/mature node, not cutting-edge (modern commercial nodes are in nanometers, e.g., 3nm/5nm) — don't overstate technological sophistication.
• eChipHub is a platform/portal, not a scheme or Act — avoid citing a non-existent statutory basis.
• Confirm the parent ministry is MeitY, not DST or Ministry of Commerce — semiconductor initiatives are sometimes wrongly attributed.

11. Sources

• [S1] NIELIT and SCL Mohali Collaborate to Make Indigenous 1.2 µm Process Design Kit Available on eChipHub — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2288610 — (tier: 1)
• [S2] Government of India to invest ₹4,500 crore for modernization of SCL Mohali; Assures that it will not be privatised — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2196011&reg=48&lang=2 — (tier: 1)