Text of PM's speech during the inauguration of SEMICON India 2026

1. At a Glance

• SEMICON India 2026 is the 5th edition of India's flagship global semiconductor conclave, inaugurated by PM Modi on 17 September 2026 at Yashobhoomi (IICC), Dwarka, New Delhi [1][3].
• It is the annual showcase event of India's push to become a global semiconductor manufacturing and design hub under the India Semiconductor Mission (ISM) [1][4].
• Jointly organised by India Semiconductor Mission (ISM) and SEMI (global semiconductor industry association), themed "Silicon to Systems: Building the Ecosystem" [3].
• Relevant for Prelims (schemes, outlays, nodal bodies) and Mains GS-III (industrial policy, self-reliance in strategic tech, electronics manufacturing).

2. Why in the News

• PM Narendra Modi inaugurated SEMICON India 2026 on 17 September 2026, delivering an address on India's semiconductor journey and ecosystem goals [1][3].
• Coincides with the rollout of India Semiconductor Mission (ISM) 2.0, announced in the Union Budget 2026-27 [5][6].
• Event held 17-19 September 2026, billed as India's biggest semiconductor event [2].

3. Background & Evolution

• Semicon India Programme approved by Union Cabinet with a total outlay of ₹76,000 crore for developing semiconductor and display manufacturing ecosystem [4].
• India Semiconductor Mission (ISM) set up as an Independent Business Division within Digital India Corporation, tasked with catalysing India's semiconductor ecosystem in manufacturing, packaging, and design [4].
• SEMICON India conclave series began earlier in the decade; SEMICON India 2025 was inaugurated by PM Modi in New Delhi (Yashobhoomi) [1].
• PM Modi separately inaugurated semiconductor manufacturing units on ground — e.g., Kaynes Semicon Plant, Sanand, Gujarat, and CG Semi OSAT facility, Sanand, Gujarat [1].
• Union Budget 2026-27 announced launch of ISM 2.0, with ₹1,000 crore provision for FY 2026-27, focused on semiconductor equipment/materials manufacturing, full-stack Indian semiconductor IP design, and supply-chain resilience [5][6].
• Modified Programme for Development of Semiconductor and Display Manufacturing Ecosystem in India has a total financial outlay of ₹8,000 crore for 2026-27 [6].

4. Core Static Facts

Item	Detail
Event	SEMICON India 2026 (5th edition)
Dates	17-19 September 2026 [2]
Venue	Yashobhoomi (India International Convention & Expo Centre), Dwarka, New Delhi [2][3]
Theme	"Silicon to Systems: Building the Ecosystem" [3]
Organisers	India Semiconductor Mission (ISM) + SEMI [3]
Nodal body	India Semiconductor Mission (ISM) — Independent Business Division under Digital India Corporation [4]
Parent Ministry	Ministry of Electronics and Information Technology (MeitY)
Original scheme outlay	Semicon India Programme — ₹76,000 crore [4]
ISM 2.0 FY27 provision	₹1,000 crore (Union Budget 2026-27) [5][6]
Modified Semicon/Display Programme outlay (2026-27)	₹8,000 crore [6]

5. Multi-Dimensional Analysis

Economic

• Aims to build a resilient domestic semiconductor value chain, reducing import dependence and creating high-value electronics manufacturing jobs [4][6].
• ISM 2.0 targets equipment/materials manufacturing and IP design — moving India up the value chain from assembly/testing to core chip design [6].

Geopolitical/Strategic

• Positions India as an alternative node in global semiconductor supply chains amid geopolitical diversification away from concentrated hubs (Taiwan, China) [3].
• International participation from global semiconductor industry stakeholders reinforces India's "trusted partner" positioning [3].

Scientific/Technological

• Focus on full-stack Indian semiconductor IP design signals a shift from foreign-licensed fabrication toward indigenous chip design capability [6].
• Complements on-ground OSAT (Outsourced Semiconductor Assembly and Test) facilities like CG Semi (Sanand) and Kaynes Semicon (Sanand) [1].

Administrative/Governance

• ISM's institutional design as a Digital India Corporation division allows faster, less bureaucratic decision-making compared to a traditional ministry wing [4].
• Sequential rollout (ISM 1.0 → Modified Programme → ISM 2.0) shows iterative policy calibration based on implementation experience [4][5][6].

6. Recent Developments (last 12-18 months)

• Union Budget 2026-27: Announced launch of ISM 2.0 with ₹1,000 crore provision [5].
• 2026: Modified Programme for Development of Semiconductor and Display Manufacturing Ecosystem allocated ₹8,000 crore for FY 2026-27 [6].
• 17 September 2026: PM Modi inaugurates SEMICON India 2026 at Yashobhoomi, New Delhi [1][3].
• Prior: PM Modi inaugurated Kaynes Semicon Plant (Sanand, Gujarat) and CG Semi OSAT facility (Sanand, Gujarat) as part of expanding domestic fabrication/assembly capacity [1].
• SEMICON India 2025: Prior edition inaugurated by PM Modi in New Delhi, showing annual cadence of the event [1].

7. Prelims Hooks

• SEMICON India 2026 was the 5th edition, held 17-19 September 2026 at Yashobhoomi, Dwarka, New Delhi [2][3].
• Theme of SEMICON India 2026: "Silicon to Systems: Building the Ecosystem" [3].
• SEMICON India is jointly organised by India Semiconductor Mission (ISM) and SEMI [3].
• ISM functions as an Independent Business Division within Digital India Corporation, not a standalone ministry/department [4].
• Original Semicon India Programme outlay: ₹76,000 crore [4].
• ISM 2.0 was announced in the Union Budget 2026-27 [5].
• ISM 2.0 FY 2026-27 budgetary provision: ₹1,000 crore [6].
• Modified Programme for Development of Semiconductor and Display Manufacturing Ecosystem outlay for 2026-27: ₹8,000 crore [6].
• ISM 2.0 focus areas: semiconductor equipment/materials manufacturing, full-stack Indian semiconductor IP design, supply-chain resilience [6].
• CG Semi OSAT facility and Kaynes Semicon Plant, both inaugurated by PM Modi, are located at Sanand, Gujarat [1].
• SEMICON India 2025 (prior edition) was also held at Yashobhoomi, New Delhi [1].
• OSAT = Outsourced Semiconductor Assembly and Test [1].
• Nodal ministry overseeing ISM: Ministry of Electronics and Information Technology (MeitY).

8. Nine of the Twelve Approved Projects Are Packaging, Not Chip-Making

• India has approved a lot of money, but mostly for the last step of the chain
• As of June 2026, 12 projects worth about ₹1.64 lakh crore were approved under ISM [7].
• Of these, only one is a silicon semiconductor fab. Two are compound semiconductor fabs. Nine are packaging units [7].

• Packaging means assembly and testing (OSAT) — taking chips made elsewhere, cutting, sealing and testing them.

• Why this matters for the value chain

• The fab is where the wafer is actually patterned. That step holds the technology and most of the profit.
• Packaging earns far less per chip and uses lower-level technology.

• So the honest reading is: India today is mostly buying a seat at the back end of the chain, not the front end. The theme "Silicon to Systems" [3] names a goal, not the present position.

• The spread across states is real, though

• Cabinet approved units in Odisha, Punjab and Andhra Pradesh with an outlay of ₹4,600 crore [10], besides the Gujarat units [1].
• So the ecosystem is no longer a one-state story — useful for a GS-III answer on balanced industrial growth.

9. The Design Scheme Asked for 100 Companies and Got 24

• The number itself
• MeitY invited applications from 100 domestic companies, startups and MSMEs under the Design Linked Incentive (DLI) Scheme (outlay ₹1,000 crore) [8].
• The scheme today supports about 24 startups, with 23 chip-design projects sanctioned [8][9].

• That is roughly a quarter of the target the scheme was built for.

• What breaks — the money comes after the spending, not before

• DLI pays up to 50% of eligible cost, capped at ₹15 crore per application [8].
• So a startup must first pay for EDA tools (the software used to design a chip) and for a tape-out (sending a finished design to a fab to be made) — and get reimbursed later.

• A small firm with no cash of its own simply cannot reach the starting line. The cap also means one expensive advanced-node design can eat the whole ₹15 crore.

• But the output is not empty

• DLI-backed firms have completed 16 tape-outs, fabricated 6 chips, filed 10 patents, and trained or engaged over 1,000 specialised engineers [8].
• Use this pair in Mains: thin participation, but real technical output from those who did get in.

10. How Far 2 Nanometre Really Is From Where India Stands

• The stated ambition
• The next phase under Semicon 2.0 sets a roadmap towards 3 nanometre and 2 nanometre technology nodes [7].

• A "node" roughly describes how small the transistors are. Smaller node = more advanced, and far harder to make.

• The gap this hides

• Commercial production has started from Micron and Kaynes plants, with two more plants due to start in 2026 [7].
• These are mature-node and packaging operations, not leading-edge logic fabs.

• Leading-edge fabs need lithography machines and ultra-pure chemicals that India does not yet make. That is exactly why ISM 2.0 names equipment and materials manufacturing as a focus [6] — the government has admitted the missing layer.

• The realistic target to quote instead

• By 2029, India is expected to be able to design and make chips for about 70–75% of domestic applications [7].
• Note the wording: domestic applications, not global leading-edge share. Most Indian demand is in autos, power, telecom and appliances — which use mature nodes, not 2nm.

11. The Strongest Argument Against Calling This Slow

• The counter-case, stated fairly
• Every chip nation started at the back end. Assembly and testing first, fabs later. Packaging-heavy approvals are the normal first rung, not a failure.
• A fab takes years from approval to wafer. India went from scheme approval to commercial production at two plants inside this cycle [7], and 12 projects worth ₹1.64 lakh crore are committed [7].

• The institutional design helps: ISM sits as an Independent Business Division inside Digital India Corporation [4], so approvals do not wait in a ministry queue.

• What is right about it, and where it still falls short

• Right: judging a semiconductor programme by year-4 output is unfair. Capacity is lumpy and arrives late.
• Still short: the risk is getting comfortable at the back end. Packaging plants can run for decades without ever forcing India to learn front-end fabrication.
• So the fair verdict is not "too slow". It is: the back end is on track, and the front end has not yet been tested.

12. What MeitY Should Change Next, and Who Did It Differently

• MeitY should pay design startups up front, not only as reimbursement
• Today DLI reimburses up to 50% of cost, capped at ₹15 crore [8], so the firm must spend first.
• A first-stage grant for EDA tool access and the first tape-out would let cash-poor MSMEs enter — the group the scheme was written for.

• Evidence it is needed: 100 firms invited, about 24 supported [8].

• ISM should treat equipment and materials as the real test of ISM 2.0

• ISM 2.0's own focus list already names semiconductor equipment and materials manufacturing and supply-chain resilience [6].
• Without these, every new fab still imports its tools, and "self-reliance" stops at the factory gate.

• Track this with one question in the exam hall: how many equipment or materials units have been approved, against nine packaging units [7]?

• MeitY should scale the talent pipeline alongside the plants

• DLI projects have trained or engaged over 1,000 specialised engineers [8]; the Chips to Start-up (C2S) Programme is the dedicated MeitY channel for building chip-design manpower in colleges [11].
• A fab needs thousands of trained process engineers, not hundreds. Plants can be approved in months; engineers take years — so the pipeline must run ahead of the plants, not behind them.

13. Anchors for Answers

• Data: 12 projects worth about ₹1.64 lakh crore approved under ISM as of June 2026 — 1 silicon fab, 2 compound semiconductor fabs, 9 packaging units [7]
• Data: DLI Scheme — ₹1,000 crore outlay, applications invited from 100 firms, about 24 startups supported, 16 tape-outs, 6 chips fabricated, 10 patents, 1,000+ engineers trained [8][9]
• Data: Target — capability to design and make chips for 70–75% of domestic applications by 2029; roadmap to 3nm and 2nm nodes under Semicon 2.0 [7]
• Data: ₹4,600 crore outlay for semiconductor units in Odisha, Punjab and Andhra Pradesh [10]
• Scheme: Design Linked Incentive (DLI) — 50% of eligible cost, capped at ₹15 crore per application; three components — chip design infrastructure, product DLI, deployment-linked incentive [8]
• Scheme: Chips to Start-up (C2S) Programme — MeitY's chip-design talent and startup pipeline [11]
• Scheme: ISM 2.0 — equipment and materials manufacturing, full-stack Indian semiconductor IP design, supply-chain resilience [6]

14. Mains Relevance

• GS-III: Indian Economy — Infrastructure, Industrial Policy; Science & Technology — indigenization of technology and developing new technology; Economic growth and development.
• GS-II (peripherally): Government policies and interventions for development in various sectors.
• Possible question stems: 1. Discuss the significance of the India Semiconductor Mission in achieving India's self-reliance in critical and emerging technologies. What challenges remain in scaling domestic chip design capability? (GS-III) 2. How does India's semiconductor manufacturing push fit into the broader global supply-chain diversification away from geographic concentration? Examine India's strategic advantages and constraints. (GS-III/GS-II) 3. Critically evaluate the evolution of India's semiconductor policy from the Semicon India Programme to ISM 2.0. (GS-III)

15. Related Topics to Study Next

• Production Linked Incentive (PLI) Scheme for electronics — parent framework enabling semiconductor manufacturing incentives.
• Digital India Programme / Digital India Corporation — institutional host of ISM.
• National Policy on Electronics — broader electronics manufacturing policy context.
• Make in India — overarching manufacturing self-reliance initiative.
• Global semiconductor supply chain geopolitics (Taiwan, US CHIPS Act) — comparative/strategic context.
• Critical Minerals Mission — upstream raw material dependency for chip manufacturing (rare earths, silicon).
• Startup India / Deep Tech Startup policy — linkage to chip design startups under ISM 2.0's IP focus.

16. Common Errors / Trap Areas

• Confusing ISM (India Semiconductor Mission) with MeitY itself — ISM is a business division under Digital India Corporation, not a ministry department [4].
• Mixing up Semicon India Programme (₹76,000 crore, original) with ISM 2.0 (₹1,000 crore FY27 provision) and the Modified Programme (₹8,000 crore for 2026-27) — these are distinct, layered allocations, not one single figure [4][5][6].
• Assuming SEMICON India is a government-only event — it is jointly organised with SEMI, a global industry association [3].
• Confusing SEMICON India (annual conclave) with India Semiconductor Mission (ongoing policy programme) — the conclave is an event; ISM is the implementing institutional mechanism.
• Misattributing plant inaugurations (e.g., Kaynes Semicon, CG Semi OSAT) to a different state — both are located in Sanand, Gujarat, not elsewhere [1].