Design Linked Incentive Scheme

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Design Linked Incentive (DLI) Scheme — UPSC Study Note

1. At a Glance

• DLI Scheme is a MeitY fiscal-support programme under the Semicon India Programme to build a self-reliant chip-design ecosystem (ICs, chipsets, SoCs, IP cores) [S1][S2].
• Targets the fabless segment, which contributes 30–35% of global semiconductor sales and up to 50% of value addition in chips [S1].
• Relevant for UPSC because it sits at the intersection of Atmanirbhar Bharat, electronics value-chain shift, and strategic tech sovereignty.

2. Why in the News

• PIB Backgrounder (04 Jan 2026) flagged scheme progress: 24 chip-design projects sanctioned; 16 tape-outs, 6 ASICs, 10 patents, 1,000+ engineers, >3× private investment leveraged [S1].
• Earlier (2025), 23 projects had been sanctioned, indicating active expansion of the pipeline [S3].

3. Background & Evolution

• Dec 2021: Union Cabinet approved the Semicon India Programme, outlay ₹76,000 crore, covering fabs, display fabs, compound semis, ATMP and design [S4].
• Dec 2021: DLI Scheme notified by MeitY with ₹1,000 crore outlay over 5 years [S2].
• Jan 2022: Applications opened; C-DAC designated as Nodal Agency [S2].
• 2023–25: futureDESIGN start-ups onboarded; project count scaled to 24 by Jan 2026 [S1][S5].

4. Core Static Facts

• Nodal Ministry: Ministry of Electronics and IT (MeitY) [S1].
• Implementing/Nodal Agency: C-DAC (Centre for Development of Advanced Computing), a scientific society under MeitY [S2].
• Parent Programme: Semicon India Programme (outlay ₹76,000 cr) [S2].
• DLI Outlay: ₹1,000 crore; Tenure: 5 years [S2].
• Beneficiaries: Domestic companies, startups, MSMEs in semiconductor design [S2].
• Three Components: 1. Chip Design Infrastructure Support — access to EDA tools, IP cores, design platforms via C-DAC [S2]. 2. Product DLI — reimbursement up to 50% of eligible expenditure, ceiling ₹15 crore per application [S2]. 3. Deployment Linked Incentive — 6% to 4% of net sales turnover over 5 years, ceiling ₹30 crore per application [S2].
• Coverage: ICs, Chipsets, SoCs, Systems & IP Cores, semiconductor-linked designs [S2].

5. Multi-Dimensional Analysis

Economic - Chip design contributes 20–50% of BOM cost of a chip; capturing it onshore reduces import dependence [S1]. - >3× private investment leveraged on government incentive — high crowding-in efficiency [S1].

Scientific / Technological - 16 tape-outs and 6 ASICs demonstrate movement from RTL design to silicon realisation [S1]. - Strategic verticals covered: drone detection, satellite communications, microprocessors, IoT SoCs, video surveillance, energy metering [S1].

Geopolitical / Strategic - Reduces exposure to Taiwan/US/China concentration in design IP; aligns with Quad semiconductor supply-chain initiatives [S1]. - Defence/space dual-use chips (satcom, drone) reinforce strategic autonomy [S1].

Administrative - Single-window through C-DAC simplifies sanction; fabless-MSME focus addresses capital scarcity at design stage [S2]. - Continuous applications model (rolling window) [S2].

6. Recent Developments (last 12-18 months)

• 2025: 23 chip-design projects sanctioned under DLI [S3].
• 04 Jan 2026 (PIB): Updated tally — 24 projects, 16 tape-outs, 6 ASICs, 10 patents, 1,000+ engineers engaged [S1].

7. Prelims Hooks

• DLI Scheme launched by MeitY in December 2021 [S2].
• DLI outlay = ₹1,000 crore (NOT ₹76,000 crore — that is parent Semicon India) [S2].
• Nodal implementing agency = C-DAC, not MeitY directly [S2].
• Product DLI ceiling = ₹15 crore/application; Deployment DLI ceiling = ₹30 crore/application [S2].
• Deployment incentive rate = 6%→4% of net sales over 5 years [S2].
• Product DLI reimburses up to 50% of eligible expenditure [S2].
• Scheme tenure = 5 years [S2].
• Fabless segment share of global semi sales = 30–35% [S1].
• Chip design value addition share = up to 50% [S1].
• As of Jan 2026: 24 projects, 16 tape-outs, 6 ASICs, 10 patents [S1].
• Strategic sectors include drone detection, satellite communications, IoT SoCs, energy metering [S1].
• DLI sits under the Semicon India Programme (₹76,000 cr Cabinet approval, Dec 2021) [S4].

8. Mains Relevance

• GS-III — Indian Economy (Industrial Policy); Science & Technology (indigenisation of frontier tech); Internal Security (supply-chain resilience).
• Syllabus heading: "Effects of liberalisation on the economy, changes in industrial policy"; "Achievements of Indians in S&T; indigenisation of technology".
• Probable stems:
• "Design, not fabrication, is where semiconductor value is captured. Examine how India's DLI Scheme positions it in the global chip value chain."
• "Discuss the architecture of the Semicon India Programme and evaluate the role of fabless incentives in achieving strategic autonomy."

9. Related Topics to Study Next

• Semicon India Programme — parent scheme (fab, display, ATMP) [S4].
• India Semiconductor Mission (ISM) — implementing body for fab incentives.
• PLI Schemes (Electronics, IT Hardware) — complementary downstream pull.
• C-DAC — its broader R&D mandate beyond DLI.
• Quad Semiconductor Supply Chain Initiative — geopolitical context.
• National Policy on Electronics 2019 — overarching ESDM policy.
• Compound Semiconductors / ATMP units — Tata-Micron projects.
• Make in India / Atmanirbhar Bharat — overarching framework.

10. Common Errors / Trap Areas

• Confusing DLI (₹1,000 cr) with Semicon India (₹76,000 cr) outlay.
• Attributing implementation to MeitY/ISM directly; nodal agency is C-DAC [S2].
• Conflating DLI (design) with PLI (production) — different schemes, different ministries' typical PLIs.
• Assuming DLI covers fabrication; it covers design + deployment, not wafer fab.
• Mixing up ceilings: Product = ₹15 cr, Deployment = ₹30 cr [S2].

11. Sources

• [S1] Design Linked Incentive Scheme — PIB Backgrounder, 04 Jan 2026 — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2211220 — (tier: 1)
• [S2] Applications invited under DLI Scheme — PIB, Jan 2022 — https://www.pib.gov.in/Pressreleaseshare.aspx?PRID=1790346 — (tier: 1)
• [S3] 23 Chip-Design Projects Sanctioned under DLI — PIB — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2150464 — (tier: 1)
• [S4] Cabinet approves Programme for Development of Semiconductors and Display Manufacturing Ecosystem — PIB, Dec 2021 — https://www.pib.gov.in/PressReleasePage.aspx?PRID=1781723 — (tier: 1)
• [S5] Two more futureDESIGN start-ups under SemiconIndia DLI — PIB — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2002752 — (tier: 1)