Chips to Start-up (C2S) Programme

1. At a Glance

• Capacity-building umbrella programme of the Ministry of Electronics & IT (MeitY) to nurture India's indigenous chip design ecosystem by training manpower and incubating fabless start-ups in VLSI/embedded design [S1][S2].
• Anchors the design pillar of India's semiconductor strategy alongside the India Semiconductor Mission (ISM) and Design Linked Incentive (DLI) scheme [S2][S3].
• High UPSC salience: tests on schemes, S&T self-reliance, electronics manufacturing, and Aatmanirbhar Bharat (GS-III) [S1].

2. Why in the News

• PIB Backgrounder (18 Jan 2026) released cumulative C2S performance: >1 lakh enrolled, ~67,000 trained, 122 design submissions from 46 institutions, 56 student-designed chips fabricated at SCL Mohali, 75+ patents filed and 500+ IP cores/ASICs/SoCs under development [S1].
• The ChipIN Centre completed 6 shared wafer runs and 265+ training sessions with industry partners [S1].

3. Background & Evolution

• Launched in 2022 by MeitY as part of the ₹76,000-crore Semicon India Programme (Dec 2021 Cabinet approval) that also created ISM and DLI [S2][S3].
• First Call for Proposals: invited from academia, R&D bodies, start-ups, MSMEs in 2022 [S2].
• Builds on the earlier Special Manpower Development Programme for Chips to System Design (SMDP-C2SD) run by MeitY [S2].
• Implementation arm: C-DAC Bengaluru through the ChipIN Centre; fabrication at Semi-Conductor Laboratory (SCL), Mohali on 180 nm node [S1][S3].

4. Core Static Facts

• Nodal Ministry: Ministry of Electronics & Information Technology (MeitY) [S2].
• Implementing Agency: C-DAC Bengaluru (ChipIN Centre); fabrication by SCL Mohali (under DoS-administered SCL, operated for MeitY use) [S1][S3].
• Outlay: ₹250 crore over 5 years [S3].
• Targets (5-year):
• Train 85,000 high-quality VLSI / Embedded System Design engineers [S3].
• Develop 175 ASICs [S3].
• Working prototypes of 20 SoCs [S3].
• Build an IP Core repository [S3].
• Coverage: ~305 academic institutions under C2S; 95 start-ups under DLI (ecosystem total ~400 orgs) [S3].
• Fabrication cadence: every 3 months, ChipIN bundles student designs and sends to SCL Mohali (180 nm CMOS) [S3].
• Eligibility: academia, R&D organisations, start-ups, MSMEs [S2].

5. Multi-Dimensional Analysis

Economic - Targets reduction in electronics import bill (semiconductors are India's 3rd-largest import after crude and gold) by creating indigenous fabless design capability [S2]. - Pipeline of 500+ IP cores/ASICs/SoCs seeds future commercial start-ups, complementing the DLI scheme [S1][S3].

Scientific / Technological - Provides EDA tool access, compute, IP cores and mentorship to institutions that otherwise cannot afford industry-grade chip design flows [S3]. - Hands-on tape-out at SCL Mohali (180 nm) democratises silicon prototyping — 56 student-designed chips fabricated is a global rarity at this scale [S1].

Strategic / Geopolitical - Embeds India in the global semiconductor supply-chain restructuring (post-COVID chip shortage; US CHIPS Act parallels) by building design talent gravity — the highest-value layer of the value chain [S2]. - Reduces strategic dependence on Taiwan/South Korea/China for design IP [S2].

Administrative / Governance - Multi-stakeholder model: MeitY (policy) + C-DAC (delivery) + SCL (fab) + academia (talent) + industry (mentorship) — a federal-academic-industry triad [S1][S3]. - Outcome-monitored: enrolment, training, submissions, patents, fabrications are publicly tracked [S1].

6. Recent Developments (last 12-18 months)

• 18 Jan 2026 (PIB): Backgrounder reported >1 lakh enrolments, ~67,000 trained, 56 fabricated chips, 75+ patents, 500+ IP/ASIC/SoC designs [S1].
• ChipIN Centre at C-DAC Bengaluru emerged as India's largest shared chip-design infrastructure [S3].
• 265+ training sessions and 6 shared wafer runs completed by Jan 2026 [S1].
• C2S progressing in tandem with ISM approvals for Micron (Sanand), Tata-PSMC (Dholera), CG Power-Renesas, Kaynes and Tata-OSAT (Jagiroad) [S2].

7. Prelims Hooks

• C2S Programme launched in 2022 by MeitY [S2].
• Outlay: ₹250 crore over 5 years [S3].
• 5-year targets: 85,000 engineers, 175 ASICs, 20 SoC prototypes [S3].
• ChipIN Centre is located at C-DAC Bengaluru [S3].
• Fabrication done at SCL Mohali on 180 nm node [S3].
• Part of the Semicon India Programme (₹76,000 crore, approved Dec 2021) [S2].
• Sister schemes: India Semiconductor Mission (ISM) and Design Linked Incentive (DLI) [S2][S3].
• ~305 academic institutions participating under C2S [S3].
• By Jan 2026: ~67,000 trained, 56 student chips fabricated, 75+ patents filed [S1].
• Predecessor: SMDP-C2SD programme of MeitY [S2].
• Eligibility extends to start-ups and MSMEs, not academia alone [S2].
• Wafer runs bundle student designs quarterly for SCL fabrication [S3].

8. Mains Relevance

• GS-III: Science & Technology — indigenisation; Indian economy — industrial policy & infrastructure; Achievements of Indians in S&T.
• GS-II: Government policies and interventions for development.
• Question stems: 1. "Indigenous chip design is the highest-value sliver of the semiconductor stack." Discuss how the C2S Programme operationalises this insight. (GS-III, 250 words) 2. Examine the complementarity between the India Semiconductor Mission, DLI and C2S in achieving semiconductor self-reliance. (GS-III) 3. Capacity building, not capital subsidy, is India's real semiconductor bottleneck. Critically evaluate with reference to C2S. (GS-III)

9. Related Topics to Study Next

• India Semiconductor Mission (ISM) — fab/ATMP incentives, sister pillar.
• Design Linked Incentive (DLI) Scheme — funds fabless start-ups graduating from C2S.
• Semicon India Programme (₹76,000 cr) — parent umbrella.
• SCL Mohali — only operational Indian fab (180 nm), the C2S tape-out partner.
• PLI Scheme for Large-Scale Electronics & IT Hardware — downstream demand for chips.
• National Quantum Mission / IndiaAI Mission — adjacent deep-tech missions of MeitY/DST.
• Aatmanirbhar Bharat in electronics — thematic umbrella.
• Global semiconductor geopolitics — US CHIPS Act, Taiwan-China, export controls.

10. Common Errors / Trap Areas

• Wrong ministry: C2S is under MeitY, NOT DST or Department of Space (SCL is operationally under DoS but C2S is a MeitY scheme) [S2].
• Confusing C2S with ISM/DLI: C2S = academic capacity-building; DLI = financial incentive to fabless start-ups; ISM = fab/ATMP incentives. All three sit under Semicon India Programme [S2][S3].
• Outlay confusion: C2S = ₹250 cr; Semicon India parent = ₹76,000 cr. Don't conflate [S2][S3].
• Fab node: SCL Mohali fabricates at 180 nm, not leading-edge nodes — easy MCQ trap [S3].
• Predecessor: SMDP-C2SD (Special Manpower Development Programme for Chips to System Design) is often mis-stated as C2S itself [S2].

11. Sources

• [S1] Chips to Start-up (C2S) Programme — PIB Backgrounder, 18 Jan 2026 — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2215755 — (tier: 1)
• [S2] MeitY invites applications under the Chips to Startup (C2S) Programme — PIB — https://www.pib.gov.in/Pressreleaseshare.aspx?PRID=1790350 — (tier: 1)
• [S3] Semiconductor start-ups in India attracting record investment — PIB — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2147821 — (tier: 1)