Union Minister Shri Ashwini Vaishnaw launches 2 nm semiconductor chip in Qualcomm in Bengaluru

1. At a Glance

• On 7 February 2026, Union Minister for Electronics & IT Shri Ashwini Vaishnaw launched a 2 nanometre (nm) semiconductor chip designed at Qualcomm's India engineering operations in Bengaluru [S1].
• The chip was designed across Qualcomm's Bengaluru, Chennai and Hyderabad centres — a milestone in India's transition from chip consumer to chip designer under the India Semiconductor Mission (ISM) [S1][S2].
• Significance for UPSC: anchors GS-III questions on deep-tech, electronics manufacturing, Atmanirbhar Bharat, 5th Industrial Revolution and critical-tech geopolitics [S1].

2. Why in the News

• Vaishnaw unveiled the Qualcomm 2 nm chip and used the platform to outline ISM 2.0 priorities: (i) design companies & startups, (ii) entire ecosystem in India, (iii) deeper talent base [S1].
• Coincides with Cabinet approval of ISM 2.0 (February 2026) and cumulative approval of 10 semiconductor projects across 6 states with ~₹1.60 lakh crore investment as of Dec 2025 [S2].

3. Background & Evolution

• Dec 2021: Cabinet approved the Programme for Development of Semiconductors and Display Manufacturing Ecosystem with outlay of ₹76,000 crore; India Semiconductor Mission (ISM) set up as an independent business division under Digital India Corporation under MeitY [S3].
• Four schemes launched: Semiconductor Fabs, Display Fabs, Compound Semiconductors/Sensors/ATMP-OSAT, and Design Linked Incentive (DLI) [S3].
• 2024: Cabinet approved Tata Electronics' fab at Dholera, Gujarat and OSAT at Morigaon, Assam; Micron's Sanand (Gujarat) ATMP; CG Power; Kaynes [S4].
• Feb 2026: ISM 2.0 approved to widen scope; Qualcomm 2 nm design tape-out announced [S1][S2].

4. Core Static Facts

• Event date / venue: 7 Feb 2026, Qualcomm campus, Bengaluru [S1].
• Minister: Ashwini Vaishnaw — holds Railways; Information & Broadcasting; Electronics & IT [S1].
• Nodal ministry: Ministry of Electronics & Information Technology (MeitY); implementing body India Semiconductor Mission (ISM) [S3].
• Programme outlay (original): ₹76,000 crore, fiscal support up to 50 % of project cost for silicon fabs, compound semis, ATMP and design [S2][S3].
• Approved units (cumulative, Dec 2025): 10 projects in 6 states; ~₹1.60 lakh crore investment [S2].
• Tata Electronics Dholera fab: >₹91,000 crore; 50,000 wafer starts/month (WSPM) [S2][S4].
• Tata Morigaon (Assam) OSAT: ₹27,000 crore; up to 48 million chips/day using flip-chip & ISIP [S2].
• Process node 2 nm: most advanced commercial logic node; designed (not fabricated) in India [S1].

5. Multi-Dimensional Analysis

Scientific / Technological - 2 nm uses gate-all-around (GAAFET) nanosheet transistors, succeeding FinFET; reflects India's strength in EDA, IP and verification even without leading-edge fabs [S1]. - Tape-out done in India shows front-end design parity with US/Taiwan/Korea teams [S1].

Economic - Electronics is targeted as a $500 bn industry by 2030; semis are the bottleneck input [S2]. - ISM 2.0 deepens DLI to seed fabless startups and reduce ~$25 bn annual chip import bill [S2].

Geopolitical / Strategic - Aligns with Quad Semiconductor Supply Chain Initiative and US-India iCET; counters concentration in Taiwan amid PRC-Taiwan tensions [S2]. - Qualcomm (US) anchoring design in India signals friend-shoring of critical tech [S1].

Administrative - Three-pronged Vaishnaw doctrine: design startups → full ecosystem → talent depth [S1]. - Centre-state co-funding: Gujarat, Assam, Karnataka, UP, MP, Odisha host approved units [S2].

Ethical / Governance - Vaishnaw framed semis under "5th Industrial Revolution" requiring govt-industry-academia triad [S1].

6. Recent Developments (last 12-18 months)

• Feb 2025: Fiscal Support Agreement signed between ISM and Tata Electronics/TSMC for Dholera fab [S4].
• Dec 2025: 10th project approval crosses ₹1.60 lakh crore aggregate [S2].
• Feb 2026: Cabinet clears ISM 2.0; Qualcomm 2 nm chip launched in Bengaluru [S1][S2].

7. Prelims Hooks

• 2 nm chip launched on 7 Feb 2026 at Qualcomm, Bengaluru by Ashwini Vaishnaw [S1].
• Nodal ministry = MeitY (not DST, not DoT) [S1].
• ISM is housed under Digital India Corporation, not as a separate statutory body [S3].
• Original semiconductor programme outlay = ₹76,000 crore (Dec 2021) [S3].
• Fiscal support under ISM = up to 50 % of project cost (uniform across nodes after 2024 revision) [S2].
• Dholera (Gujarat) hosts India's first commercial silicon fab by Tata Electronics + PSMC (Taiwan) [S2][S4].
• Morigaon (Assam) = Tata OSAT, 48 million chips/day capacity [S2].
• Sanand (Gujarat) = Micron ATMP, first approved unit [S2].
• DLI scheme targets fabless design startups [S3].
• Qualcomm's Indian design centres: Bengaluru, Chennai, Hyderabad [S1].
• Vaishnaw also holds Railways and I&B portfolios [S1].
• Vaishnaw's "three focuses": design firms/startups, full ecosystem, talent depth [S1].

8. Mains Relevance

• GS-III: Science & Technology — Indigenisation; Achievements of Indians in S&T; Awareness in new tech.
• GS-III: Economy — Industrial policy, Atmanirbhar Bharat, MSME/startups.
• GS-II: International Relations — Bilateral (US-India iCET, Quad).
• Possible stems: 1. "Designing chips is necessary but not sufficient for semiconductor self-reliance." Examine in light of ISM 2.0. 2. Critically evaluate the three-pronged strategy outlined for India's semiconductor ecosystem under ISM 2.0. 3. How does the India Semiconductor Mission integrate with India's broader Quad and iCET commitments?

9. Related Topics to Study Next

• DLI Scheme — direct vehicle for the "design-first" pillar Vaishnaw highlighted.
• PLI for Large-Scale Electronics & IT Hardware — complementary downstream demand pillar.
• iCET (India-US initiative on Critical & Emerging Tech) — geopolitical wrapper for semis.
• Quad Semiconductor Supply Chain Initiative — multilateral angle.
• National Quantum Mission — sibling deep-tech mission under DST.
• Digital India Corporation — parent of ISM; governance pattern.
• Critical Minerals Mission (2025) — upstream input (Ga, Ge, rare earths) for chips.
• Tata Electronics Dholera fab / Micron Sanand ATMP — flagship project facts.

10. Common Errors / Trap Areas

• The chip was designed, not fabricated, in India — India still has no operational 2 nm fab [S1].
• ISM is under MeitY, not Department of Science & Technology or Department of Telecom.
• Original outlay ₹76,000 crore refers to the 2021 programme, not ISM 2.0 (separate, additional).
• Dholera fab is by Tata Electronics + PSMC (Taiwan), not TSMC.
• ISM is an independent business division of Digital India Corporation, not a statutory authority created by Act of Parliament.

11. Sources

• [S1] Union Minister Shri Ashwini Vaishnaw launches 2 nm semiconductor chip in Qualcomm in Bengaluru — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2224990 — (tier: 1)
• [S2] India Semiconductor Mission 2.0 — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2224839 — (tier: 1)
• [S3] Cabinet approves Programme for Development of Semiconductors and Display Manufacturing Ecosystem in India (Dec 2021) — https://www.pib.gov.in/PressReleasePage.aspx?PRID=1781723 — (tier: 1)
• [S4] ISM, Tata Electronics & Tata Semiconductor Manufacturing sign Fiscal Support Agreement — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2108602 — (tier: 1)