DLI Scheme-Backed Chip Design Startups Continue to Attract Interest from Leading Investors

I have sufficient facts from Tier 1 (PIB / MeitY). Producing the study note.

DLI Scheme-Backed Chip Design Startups — UPSC Study Note

1. At a Glance

• Design Linked Incentive (DLI) Scheme is MeitY's flagship instrument to nurture an indigenous semiconductor/chip design ecosystem of startups, MSMEs and domestic firms [S1][S2].
• Implemented through C-DAC as nodal agency; offers fiscal support + access to EDA tools / IP cores across a 5-year window [S2].
• UPSC relevance: intersects GS-III (S&T, indigenisation, industrial policy), economy (FDI, VC inflows), and strategic autonomy (chip sovereignty under India Semiconductor Mission) [S1][S3].

2. Why in the News

• 16 Feb 2026 PIB release: Bengaluru-based C2i Semiconductors (a DLI-backed startup) raised US$15 million Series A led by Peak XV Partners — the largest funding round by an Indian semiconductor startup [S1].
• C2i is designing an intelligent power-management chip for energy-efficient High-Performance Computing (HPC) / AI data centres [S1].
• Signals maturation of post-2021 VC interest in Indian fabless/chip-design ecosystem [S1].

3. Background & Evolution

• 2021 (Dec): Union Cabinet approved the ₹76,000 crore Programme for Development of Semiconductors and Display Manufacturing Ecosystem; India Semiconductor Mission (ISM) set up [S4].
• 2021–22: DLI Scheme announced by MeitY as one of the four sub-schemes (along with Semiconductor Fab, Display Fab, Compound Semiconductors/ATMP) [S2].
• 2022 onwards: C-DAC notified as nodal agency; applications invited from 100 domestic firms/startups/MSMEs [S2].
• 2024–25: 23 chip-design projects sanctioned under DLI [S2].
• 2026 (Jan): 24 startups under DLI; cumulative ~₹430 crore VC raised by DLI-backed firms [S3].
• 2026 (Feb): India Semiconductor Mission 2.0 announced [S3].

4. Core Static Facts

• Scheme: Design Linked Incentive (DLI), also called SemiconIndia futureDESIGN [S2].
• Parent Ministry: Ministry of Electronics & Information Technology (MeitY) [S1][S2].
• Nodal/Implementing Agency: Centre for Development of Advanced Computing (C-DAC) — scientific society under MeitY [S2].
• Duration: 5 years from launch [S2].
• Three Components [S2]: 1. Chip Design Infrastructure Support — access to EDA tools, IP cores via C-DAC. 2. Product DLI — reimbursement up to 50% of eligible expenditure, ceiling ₹15 crore per application. 3. Deployment Linked Incentive — 6%→4% of net sales over 5 years, ceiling ₹30 crore per application.
• Scope of Design: ICs, Chipsets, SoCs, Systems, IP Cores, semiconductor-linked design [S2].
• Target: ~100 domestic firms/startups/MSMEs [S2].
• Umbrella Programme: ₹76,000 crore Semicon India Programme (2021) [S4].

5. Multi-Dimensional Analysis

Economic - VC investment in Indian semiconductor sector was negligible pre-2021; DLI-backed firms have now drawn ~₹430 crore [S1][S3]. - C2i's US$15 mn round signals derisking of the fabless model in India [S1]. - Reduces import dependence; India's electronics import bill remains among the largest after crude [S4].

Scientific / Technological - DLI targets fabless design — high-value, IP-intensive segment (vs. capital-heavy fabrication) [S2]. - C2i's focus on power-management chips for AI/HPC aligns with global thrust on energy-efficient compute [S1]. - Centralized EDA tool access via C-DAC lowers >US$ million tool-licence barrier for startups [S1][S2].

Strategic / Geopolitical - Chips are a strategic commodity; DLI complements ISM, Compound Semi/ATMP scheme, and Modified SPECS [S4]. - Supports trusted supply chains alignment with Quad/US CHIPS Act ecosystem.

Administrative - Single-window via C-DAC; Empowered Committee under MeitY clears applications [S2]. - Bottlenecks: long gestation, talent gap (only ~65 engineers at top firm C2i) [S1].

6. Recent Developments (last 12-18 months)

• Nov 2024: C2i Semiconductors approved under DLI [S3].
• 2024–25: 23 chip-design projects sanctioned under DLI [S2].
• 2025: Union Minister Ashwini Vaishnaw interacted with DLI-approved chip design firms [S2].
• Jan 2026: DLI cohort reaches 24 startups; ~₹430 cr VC mobilised [S3].
• Feb 2026: India Semiconductor Mission 2.0 unveiled [S3].
• 16 Feb 2026: C2i closes US$15 mn Series A led by Peak XV — largest by an Indian semi startup [S1].

7. Prelims Hooks

• DLI Scheme is implemented by MeitY, not DST or DSIR [S2].
• Nodal agency: C-DAC [S2].
• Product DLI ceiling: ₹15 crore, up to 50% of eligible expenditure [S2].
• Deployment Linked Incentive ceiling: ₹30 crore, 6%→4% of net sales over 5 years [S2].
• DLI is part of the ₹76,000 cr Semicon India Programme approved by Cabinet in December 2021 [S4].
• Also branded SemiconIndia futureDESIGN [S2].
• C2i Semiconductors — Bengaluru-based; incorporated 5 June 2024 [S3].
• C2i's Series A: US$15 million, lead investor Peak XV Partners (announced 16 Feb 2026) [S1].
• DLI covers ICs, Chipsets, SoCs, Systems & IP Cores [S2].
• India Semiconductor Mission (ISM) is an independent business division within Digital India Corporation under MeitY [S4].
• 24 DLI-supported startups as of Jan 2026 [S3].

8. Mains Relevance

• GS-III — Science & Technology (indigenisation of strategic tech); Economy (industrial policy, FDI).
• Syllabus headings: "Awareness in the fields of IT, Space, Computers… Indigenisation of technology"; "Effects of liberalisation on the economy… industrial policy".
• Plausible question stems: 1. "Examine how the Design Linked Incentive Scheme addresses structural weaknesses in India's semiconductor value chain." 2. "Fabless design, not fabrication, is India's pragmatic entry point into the global semiconductor industry. Discuss." 3. "Discuss the role of MeitY and C-DAC in catalysing private venture capital for deep-tech startups, with reference to the DLI Scheme."

9. Related Topics to Study Next

• India Semiconductor Mission (ISM) & ISM 2.0 — parent umbrella [S3][S4].
• Modified Semiconductor Fab / Display Fab Scheme — sister scheme [S4].
• SPECS & PLI for Electronics — adjacent demand-side support.
• Chips-to-Startup (C2S) Programme — talent pipeline complementing DLI [S2].
• Tata-PSMC Dholera fab & Micron ATMP Sanand — downstream manufacturing.
• National Quantum Mission / IndiaAI Mission — fellow deep-tech missions.
• C-DAC — its expanded mandate.
• Global comparisons — US CHIPS Act, EU Chips Act, Taiwan's TSMC model.

10. Common Errors / Trap Areas

• Wrong ministry: DLI is MeitY, not Department of Science & Technology or DPIIT.
• DLI ≠ PLI: DLI is design-focused; the ₹76,000 cr programme also has separate fab/ATMP incentives — don't conflate.
• Nodal agency confusion: C-DAC implements DLI; ISM (within Digital India Corporation) oversees fab/ATMP — different verticals.
• C2i Semiconductors ≠ C-DAC; C2i is a private Bengaluru startup, not a govt body.
• Programme outlay ₹76,000 cr is for the whole Semicon India Programme, not DLI alone.

11. Sources

• [S1] DLI Scheme-Backed Chip Design Startups Continue to Attract Interest from Leading Investors (PIB, 16 Feb 2026) — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2228508 — (tier 1)
• [S2] Government pushes semiconductor design innovation with the DLI Scheme / 23 Chip-Design Projects Sanctioned (PIB, MeitY) — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2159727 & https://www.pib.gov.in/PressReleasePage.aspx?PRID=2150464 — (tier 1)
• [S3] India Semiconductor Mission 2.0 (PIB, Feb 2026) — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2224839 — (tier 1)
• [S4] Cabinet approves Programme for Development of Semiconductors and Display Manufacturing Ecosystem (PIB, Dec 2021) — https://www.pib.gov.in/PressReleasePage.aspx?PRID=1781723 — (tier 1)