Examine how India's semiconductor policy has evolved from ISM 1.0 to Semicon 2.0. How does this align with the goals of Atmanirbhar Bharat?
In this answer
The Union Cabinet's approval of Semicon 2.0 with an outlay of ₹1,27,500 crore [1] marks a shift from merely attracting a first fabrication plant to building a full ecosystem — a move from assembly-led to capability-led self-reliance.
Evolution of scale and scope
- ISM 1.0 (2021): a ₹76,000 crore programme centred on silicon and display fabs, offering fiscal support of up to 50% of project cost, with the India Semiconductor Mission created under MeitY to drive it [2].
- Semicon 2.0: a near-doubled outlay built on six pillars — design, machines and materials, fabs, ATMP/OSAT packaging, R&D and talent [1]. Equipment and materials are a wholly new front.
- Design deepened: the Design Linked Incentive Scheme targets 100 domestic design firms, at least 20 crossing ₹1,500 crore turnover [3].
- Proof of concept: 12 units with cumulative investment over ₹1.64 lakh crore are approved [1]; commercial production has begun at Micron and Kaynes, with a roadmap towards 3nm/2nm nodes [4].
Alignment with Atmanirbhar Bharat
- Import substitution: India was a net chip importer of USD 23.5 billion in 2024 [5]; domestic fabs directly address this dependence.
- Ownership, not just employment: about 20% of the world's chip-design engineers work in India, yet domestic design revenue stays under ₹150 crore [5] — Semicon 2.0's IP and design pillar targets precisely this gap.
- Strategic autonomy: it reduces exposure to a supply chain concentrated in Taiwan and South Korea, and 315 universities with roughly 68,000 students trained build the skill base [3].
Gaps that qualify the claim
- Absorption is weak — fund utilisation was 23% (2023-24) and 9% (2024-25) [5].
- Only one approved project is a silicon fab; process technology is largely licensed from foreign partners [5].
- NITI Aayog finds a 14–18% cost disadvantage against China in components [5].
Semicon 2.0 thus converts a fab-chasing scheme into an ecosystem mission, correctly reading self-reliance as ownership of design, equipment and talent rather than output alone. Pairing it with faster single-window clearances and duty rationalisation, as NITI Aayog urges [5], would let the outlay translate into genuine technological sovereignty.
Sources
- 1Cabinet approves Semicon 2.0, PIB (2026)₹1,27,500 crore outlay, six pillars, 12 approved units worth ₹1.64 lakh crore
- 2Cabinet approves Programme for Development of Semiconductors and Display Manufacturing Ecosystem in India, PIB (2021)₹76,000 crore ISM 1.0, fab focus, 50% project-cost support
- 3Design Linked Incentive (DLI) Scheme, PIBDLI targets; 315 universities and ~68,000 students trained
- 4India Semiconductor Mission 2.0, PIBMicron and Kaynes commercial production; 3nm/2nm roadmap
- 5Demand for Grants 2026-27 Analysis: Electronics and Information Technology, PRS Legislative Researchfund utilisation, import bill, design-revenue gap, cost disadvantage, NITI Aayog recommendations
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