Semiconductor manufacturing is capital-, water-, and technology-intensive. Critically evaluate India's preparedness to compete in the global semiconductor value chain.
In this answer
India was a net importer of chips worth USD 23.5 billion in 2024, with barely 0.02% of global chip exports [3]. The ₹1,27,500 crore Semicon 2.0 outlay [2] signals serious intent, but preparedness is uneven — strong at the ecosystem's periphery, thin at its capital- and technology-intensive core.
Grounds for confidence
- Capital mobilised: 12 manufacturing units approved with cumulative investment over ₹1.64 lakh crore; Micron, Kaynes and CG Semi have begun commercial production [2].
- Design and talent base: 24 design projects supported and 105 startups given EDA-tool access under DLI [2]; 315 universities and ~68,000 students trained in chip design [4].
- Policy precedent: electronics PLI lifted smartphone and telecom exports from about USD 7 billion (2022) to USD 22 billion (2024) [3].
Capital intensity: announced is not absorbed
- Fund utilisation was only 23% (2023-24) and 9% (2024-25) [3]; ISM 2.0 received just ₹1,000 crore in 2026-27 [1].
- Finance costs run 5–6 percentage points above international rates, leaving a 14–18% cost disadvantage in components and 10–14% in assembly versus China (NITI Aayog) [3].
Technology intensity: borrowed, not owned
- Only Tata's Dholera plant is a silicon fab; the rest are ATMP/packaging units at the lowest rung of value addition [3].
- Process know-how comes from PSMC, Renesas and Foxconn [3]; 3nm/2nm remains a roadmap target, not capability [1].
- India hosts ~20% of the world's design engineers, yet domestic design revenue is under ₹150 crore — the IP accrues abroad [3].
Water, power and clustering
- A modern fab costs about USD 10 billion and needs uninterrupted water and power; Taiwan's clusters offer 0% VAT, a 17% tax cap and assured utilities, which Indian clusters have not matched [3].
- OECD finds subsidies rose globally after 2020 without firms relocating fabs home (2017–23), warning of non-additionality and subsidy races [5].
India is therefore competitive in design and packaging, but not yet in fabrication. Rationalising inverted duties, extending the National Single Window System across all three tiers of government, and building utility-secure clusters [3] will matter more than larger outlays. Judged over a decade rather than a budget cycle, Semicon 2.0 can convert strategic necessity into genuine competitive capability.
Sources
- 1India Semiconductor Mission 2.0, PIBISM 2.0 announcement, ₹1,000 crore FY 2026-27 provision, 3nm/2nm roadmap
- 2Cabinet approves Semicon 2.0, PIB₹1,27,500 crore outlay, 12 approved units and ₹1.64 lakh crore investment, Micron/Kaynes/CG Semi production, 24 design projects and 105 startups
- 3Demand for Grants 2026-27 Analysis: Electronics and IT, PRS Legislative Researchfund-utilisation shortfall, import bill and export share, cost disadvantage and finance costs, fab-versus-ATMP composition, technology partners, design-revenue gap, Taiwan comparison, PLI outcomes, NITI Aayog single-window and duty recommendations
- 4Design Linked Incentive (DLI) Scheme, PIB315 universities and ~68,000 students trained in chip design
- 5Recent Trends in Semiconductor Subsidies, OECD (April 2025)global subsidy growth without relocation of fabs; additionality and subsidy-race risks